1. Field of the Invention
The present invention generally relates to a frequency divider, and more particularly to a dual-modulus divide-by-N/(N+0.5) frequency divider adaptable for a phase locked loop (PLL).
2. Description of the Prior Art
Phase locked loop (PLL) is widely utilized in integrated circuits or systems, such as communication systems, to synchronize the clocks of a receiver. FIG. 1 shows a block diagram of the PLL. A frequency divider 10 divides (or decreases) the frequency of the output signal of a voltage controlled oscillator (VCO) 12. The frequency-divided signal and a reference signal 14 are fed to a phase detector 16 to detect their phase difference. The detected difference signal passes through a loop filter 18 to have its noise filtered out, and then controls the frequency of the output signal of the VCO 12.
The frequency divider 10 forms a negative feedback loop in the PLL of FIG. 1 to lock the VCO 12 at a multiple of the reference frequency 14. In modern communication systems, the frequency divider 10 is further required to be capable of locking the VCO 12 at and switching among various frequencies, realizing a frequency synthesizer. FIG. 2 shows a conventional dual-modulus divide-by-N/(N+1) frequency divider, which could divide the frequency of an input clock by a factor N or N+1, N being an integer. This type of frequency divider, accordingly, is commonly named an integer frequency divider. Here is an exemplary divide-by-2/3 frequency divider using a D-type flip-flop (DFF) 20 for division by 2, and another D-type flip-flop (DFF) 22 for division by 3.
FIG. 3 shows a conventional dual-modulus divide-by-N/(N+1) frequency divider adaptable for the PLL. This frequency divider includes a dual-modulus frequency-dividing circuit 30, a programmable counter 32, and a swallow counter 34. Assume the count set value of the programmable counter 32 is P, and the count set value of the swallow counter 34 is S. The swallow counter 34 counts S times of periods with division ratio of (N+1), and the programmable counter 32 subsequently counts (P−S) times of periods with division ratio of N. Accordingly, the total number of input pulses during an entire cycle of the programmable counter 32 and the swallow counter 34 are expressed as follows:(N+1)·S+N·(P−S)=P·N+S  (1)
The integer frequency divider discussed above is not sufficient for modern complex communication systems, such as wireless communication systems. For example, as the channel spacing has 200 kHz (such as in the GSM system), the reference frequency 14 (FIG. 1) should be no more than 200 kHz; and, as a rule of thumb, the bandwidth of the loop filter 18 should be no larger than one tenth of the reference frequency 14 for the stability issue. Nevertheless, a larger bandwidth of the loop filter 14 implies a faster locking time; and, furthermore, the noise due to the VCO 12 could be minimized by having the bandwidth of the loop filter 18 as wide as possible.
With respect to the above constraints, some non-integer or fractional frequency dividers are accordingly proposed. For example, a fractional frequency divider (FIG. 4A) is disclosed in U.S. Pat. No. 5,729,179, which uses COUNTER and COINCIDENCE CIRCUIT, resulting in a circuit that is complicated, high-cost, and area consuming. Another factional frequency divider (FIG. 4B) is disclosed in US Patent Publication No. 2007/0147571, which uses four level-triggered latches to make up a 1/1.5 frequency divider. As the signal out of this frequency divider receives no substantial reduction in frequency (with division ratio of 1 or 1.5), succeeding (integer) frequency divider or dividers with high division ratio are thus required.
For the reasons discussed above, a need has arisen to propose a novel dual-modulus divide-by-N/(N+0.5) frequency divider, which is capable of performing either integer frequency division or fractional frequency division. Moreover, a programmable divide-by-N/(N+0.5) frequency divider is needed for dynamically changing the value of N to be adaptable for modern complex communication systems.